1. Technical Field of the Invention
This invention relates to peripheral component interfaces. More particularly, it relates to implementing private devices on a secondary PCI or PCI-X bus and to monitoring progress of initialization sequences by a central system resource.
2. Background Art
During a normal system initialization sequence, a central system resource performs multiple PCI or PCI-X configuration commands to detect and initialize all PCI or PCI-X devices and bridges. High function adapters which include a processor and multiple chips are often implemented on a PCI or PCI-X bus that is attached to the system via a bridge. In such adapters, it is often desirable to “hide” the devices on the secondary bus from the central resource and allow their initialization to be handled by the processor contained on the adapter.
There are two types of configuration commands executed on a PCI or PCI-X bus: Type 0 and Type 1. A Type 0 configuration transaction is used to access a device on the current bus segment and a Type 1 configuration transaction is used to access a device that resides behind a bridge. What type of configuration transaction is being executed is, for example, distinguished by address bits on an A/D bus. If, for example, address bits AD [1::0] are 00b during a configuration transaction, a Type 0 configuration is being used. If address bits AD[1::0] are 01b, a Type 1 configuration is being used. A Type 0 configuration transaction is not forwarded across a bridge from its primary interface to its secondary interface, but is used to configure a bridge or other PCI devices that are connected to the PCI bus on which the Type 0 configuration transaction is generated. A Type 1 configuration transaction is used to address a device that does not reside on the current bus segment and may be forwarded to another bus segment by a bridge.
A bridge only responds to Type 0 configuration transactions on its primary PCI interface when being configured, ignores configuration transactions that originate on its secondary interface, and does not implement IDSEL on its secondary interface. During a Type 1 configuration transaction, a bridge compares a PCI bus number in address bits on the address/data bus, and determines from configuration registers if that bus number is one which the bridge should claim and forward across the bridge.
A PCI interface includes a pin designated initialization device select (IDSEL) which is used as a chip, or device, select during configuration read and write transactions. How a system generates IDSEL is system specific, but by convention this may be done as follows. During the address phase of a Type 0 configuration transaction, the IDSEL signal associated with device number 0 is connected to address/data bus AD[16], IDSEL of device number 1 is connected to AD[17], and so on until IDSEL of device number 15 is connected to AD[31].
There is a need in the art for an improved process to selectively prevent, or thwart, IDSEL generation in order to implement private devices. Existing approaches for implementing private devices block the activation of IDSEL pins according to the contents of a special mask register.
It is an object of the invention to provide an improved system and method for allowing initialization of devices on an adapter to be handled by a processor contained on the adapter.
It is a further object of the invention to provide a system and method for selectively preventing interface device selection generation in order to implement private devices on a PCI bus or the like.
It is a further object of the invention to provide a system and method for hiding devices on secondary bus from a central resource to allow their initialization to be handled by a processor on that secondary bus.